The present invention relates to a magnetic domain (magnetic bubble) device for use as a memory and the like.
It is well known that when a uniform bias magnetic field of an appropriate intensity is applied perpendicularly to the surface of a magnetic medium such as garnet having a uniaxial magnetic anistropy and the easy magnetization axis perpenducular to the surface, a magnetic bubble surrounded by a single magnetic wall whose magnetization is reversed to that in the adjacent bubble, is formed. By giving a magnetic field gradient to this bubble, the bubble moves along the gradient magnetic field. This nature enables the realization of a magnetic storage device, and also the designing of a logic circuit element becomes possible by utilizing the fact that a magnetic repulsive force is exerted upon one another between two or more magnetic bubbles.
To design a magnetic storage device using magnetic bubbles, a major-minor loop organization, a decoder organization, etc. have been adopted at present. Briefly describing the major-minor loop organization which is most frequently used now among those organizations, this organization is formed of two kinds of closed loops, that is, memory loops for storing information which are called minor loops and a propagation loop for writing in and reading out information which is called a major loop. The major loop is provided with a generator, a detector and an annhilator for the magnetic bubbles. The transfer of information between said major loop and said minor loops is controlled through a gate. Such a major-minor loop organization is disclosed, for instance, in FIG. 1 of U.S. Pat. No. 3,618,054.
To construct a magnetic bubble storage device using such a major-minor loop organization, the following three conditions must be satisfied. Assuming that the number of bits in the major loop is N.sub.Mb while the number of bits in one minor loop is N.sub.mb, the following condition must be satisfied in order to make a magnetic bubble come again to the same address position in the minor loop upon rewriting: EQU N.sub.Mb =nN.sub.mb -N.sub.gb (n: an integer), (1)
where N.sub.gb represents the number of bits needed for transferring through a gate, and in the case of the conventional Y--Y gates or dollar sign gates, generally N.sub.gb =1. In addition, to shorten the access time and the cycle time, n=1 is desirable. As a result, the first condition takes the following form: EQU N.sub.Mb =N.sub.mb -1 (2)
Secondly, if the number of the minor loops is represented by N.sub.m, the value of N.sub.m should take an integral power of 2 in view of the data construction, that is, it is necessary to meet the following condition: EQU N.sub.m =2.sup.k (k: an integer) (3)
Moreover, in general, the storage device should preferably take a square shape or an approximately square shape, and as a result, if it is attempted to form the major-minor loop also in such a shape, the following third condition must be met: EQU N.sub.mb =4N.sub.m ( 4)
To satisfy the above-mentioned three equations (2), (3) and (4) is a basic prerequisite for the adoption of the major-minor loop organization. Especially, on the basis of equations (3) and (4), equation N.sub.mb =2.sup.k+2 can be derived so that the number of bits in the minor loop also becomes an integral power of 2, and consequently, in view of the functions of a binary address counter or the like in peripheral circuits a remarkably improved major-minor loop organization can be attained.
However, as a practical matter, the following problems occur in a magnetic bubble storage device satisfying the above-mentioned three conditions. For instance, considering now a 64-kilobit (64-K bit) storage device as one example, N.sub.m =128, N.sub.mb =152 and N.sub.Mb =511 are determined according to equations (2), (3) and (4), and so, the pattern arrangement is as shown in FIG. 1. In this figure, reference numeral 1 designates a major loop, numeral 2 designates minor loops, and numeral 3 designates gates. A small circle in the major loop 1 represents a 1-bit pattern. However, the respective half-bit patterns at corner portions 11 and 12 in the major loop 1 are omitted from the illustration. It is noted here that the number of the gates 3 must be selected equal to the number of the minor loops 2, and that in the case of connecting the minor loops 2 to the major loop 1, the connection can be made only for alternate ones of the bit pattern in the major loop 1 in view of the shape of the minor loops 2. More particularly, when 128 minor loops 2 are connected to a major loop 1 via 128 gates 3, 255 bits of the 511 bits in a major loop 1 is used for that purpose. Furthermore, from the restriction on the arrangement of the generator, detector and the like for magnetic bubbles, it is desirable for the gates 3 to be aligned on one side of the major loop 1 so that on the opposite side of the major loop 1 with respect to the gates 3 is also formed a bit pattern equivalent to 255 bits. Accordingly, two corner portions 11 and 12 of the major loop 1 must be composed of the remaining one bit, and this results in a pattern arrangement having a considerably small margin. Actually, when an operating margin for a bias magnetic field in a magnetic bubble storage device having the above-mentioned construction was measured, it proved that since the sections of the major loop connected to the gates at the opposite ends and the corner portions of the major loop were too close to each other, a margin width of the bias magnetic field was small as represented by a curve B in FIG. 4, resulting in an unstable operation. Also, the addition of redundant minor loops as a measure for deficient minor loops which occur unavoidably in the case of forming the major-minor loop organization, is quite impossible in the conventional construction.
So far, in order to solve these problems, the following method has been mainly adopted. In this method, the number of bits in the minor loop is increased so that a larger number of bits may be used in the major loop, whereby the pattern arrangement is allowed to have a larger margin. However, this method can not satisfy the condition as defined by equation (4) above, and accordingly, there is a disadvantage that the number of bits in the minor loop does not become an integral power of 2, complicating the peripheral circuits.